1. Field of the Invention
The present invention relates to a semiconductor memory device, e.g., a dynamic random access memory (DRAM), having a data holding mode using an ECC function.
2. Description of the Related Art
A conventionally known example of semiconductor memory devices of this type is “a data holding method of a dynamic RAM and a semiconductor integrated circuit device” disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-56671. This patent reference has proposed a method of correcting an error bit as follows at the start of an operation mode in which a DRAM performs only a data holding operation. That is, when this operation mode starts, parity bits (or check bits) for detecting and correcting errors are generated and stored for a plurality of data, and refresh is performed by extending the refresh period within the error occurrence allowable range of an error correcting operation using the parity bits. Before the data holding operation returns to a normal operation, error bits are corrected by using the data and parity bits.
FIG. 23 of the patent reference described above is a timing chart showing timings from the end of an entry operation to the start of the data holding mode, and timings from the data holding mode to the start of an exit operation. In this method, read of data from all memory cells and write of generated parity bits are performed in an entry period during which the normal operation changes to the data holding mode. Also, in an exit period during which the data holding mode changes to the normal operation, codes, i.e., information bits and the parity bits are read out from all the memory cells, errors are detected and corrected, and the corrected data is rewritten.
Since, however, these operations are performed for all the memory cells, the transition time from the start of the exit operation to the start of the normal operation is very long.